Discussion:
riscv: how to running coreboot on HiFive Unleashed?
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王翔
2018-11-26 07:32:29 UTC
Permalink
I try to running coreboot on HiFive Unleashed, but nothing come from uart.


I tested by the following steps:


1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card.
2. Change MSEL to 11 and boot linux
3. Copy coreboot.rom via scp
4. Write coreboot.rom to /dev/mtd0 by flashcp.
5. Change MSEL to 15 and boot coreboot. No response on uart.



Do you have any suggestions?




------------------



王翔

安党研究员

广州垂腟埡安信息科技有限公叞





广州垂倩河区珠江新城华穗路406号保利克掛绎二期䞭景A座1020-1024
Jonathan Neuschäfer
2018-11-26 10:03:07 UTC
Permalink
Hi!
Post by 王翔
I try to running coreboot on HiFive Unleashed, but nothing come from uart.
1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card.
2. Change MSEL to 11 and boot linux
3. Copy coreboot.rom via scp
4. Write coreboot.rom to /dev/mtd0 by flashcp.
5. Change MSEL to 15 and boot coreboot. No response on uart.
Do you have any suggestions?
How did you listen to the UART? Note that the FTDI Chip on the H5U will
show up as two serial ports on the computer that it is connected to
(usually /dev/ttyUSB0 and /dev/ttyUSB1). The first one is for JTAG and
the second one is for UART.
Also make sure that you configure the right baud rate (115200 usually)
on /dev/ttyUSB1.

You might also have to power-cycle the board and/or press the reset
button. Sometimes that helps.

If you continue to see no output, perhaps there is a bug in coreboot
that prevents the output. Whenever I tested coreboot on the H5U, I could
always see output, but I haven't tested it recently.



Jonathan NeuschÀfer
王翔
2018-11-27 02:56:41 UTC
Permalink
I am sure my uart configuration is 115200 8N1 on /dev/ttyUSB1. I have a power cycle after the burn is complete.



圚2018幎11月26 18时03分, "Jonathan NeuschÀfer"<***@gmx.net>写道:

Hi!
Post by 王翔
I try to running coreboot on HiFive Unleashed, but nothing come from uart.
1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card.
2. Change MSEL to 11 and boot linux
3. Copy coreboot.rom via scp
4. Write coreboot.rom to /dev/mtd0 by flashcp.
5. Change MSEL to 15 and boot coreboot. No response on uart.
Do you have any suggestions?
How did you listen to the UART? Note that the FTDI Chip on the H5U will
show up as two serial ports on the computer that it is connected to
(usually /dev/ttyUSB0 and /dev/ttyUSB1). The first one is for JTAG and
the second one is for UART.
Also make sure that you configure the right baud rate (115200 usually)
on /dev/ttyUSB1.

You might also have to power-cycle the board and/or press the reset
button. Sometimes that helps.

If you continue to see no output, perhaps there is a bug in coreboot
that prevents the output. Whenever I tested coreboot on the H5U, I could
always see output, but I haven't tested it recently.



Jonathan NeuschÀfer
王翔
2018-11-27 04:20:53 UTC
Permalink
I tried it again. Press reset key can see the serial output. Maybe the power is turned on too fast. The computer does not capture the serial port data.

Below is my serial output
Welcome to minicom 2.7
OPTIONS: I18n
Compiled on Apr 22 2017, 09:14:19.
Port /dev/ttyUSB1, 12:14:37
Press CTRL-A Z for help on special keys
coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock starting...
Boot mode: 15
Couldn't load romstage.
Thank you for your help.


圚2018幎11月27 10时56分, "王翔"<***@126.com>写道:


I am sure my uart configuration is 115200 8N1 on /dev/ttyUSB1. I have a power cycle after the burn is complete.



圚2018幎11月26 18时03分, "Jonathan NeuschÀfer"<***@gmx.net>写道:

Hi!
I try to running coreboot on HiFive Unleashed, but nothing come from uart.
1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card.
2. Change MSEL to 11 and boot linux
3. Copy coreboot.rom via scp
4. Write coreboot.rom to /dev/mtd0 by flashcp.
5. Change MSEL to 15 and boot coreboot. No response on uart.
Do you have any suggestions?
How did you listen to the UART? Note that the FTDI Chip on the H5U will
show up as two serial ports on the computer that it is connected to
(usually /dev/ttyUSB0 and /dev/ttyUSB1). The first one is for JTAG and
the second one is for UART.
Also make sure that you configure the right baud rate (115200 usually)
on /dev/ttyUSB1.

You might also have to power-cycle the board and/or press the reset
button. Sometimes that helps.

If you continue to see no output, perhaps there is a bug in coreboot
that prevents the output. Whenever I tested coreboot on the H5U, I could
always see output, but I haven't tested it recently.



Jonathan NeuschÀfer
Jonathan Neuschäfer
2018-11-27 12:27:03 UTC
Permalink
Post by 王翔
I tried it again. Press reset key can see the serial output. Maybe the
power is turned on too fast. The computer does not capture the serial
port data.
Unfortunately, the FTDI chip is also behind the power button, so when
you release the power button, the FTDI chip starts up, and minicom has
to reconnect, and at the same time the SoC already starts running and
printing things on the UART.

Something like this helps sometimes:

- Power the board off via the power button
- Press and hold the reset button
- Power the board on
- Wait until minicom has reconnected
- Release the reset button
Post by 王翔
Below is my serial output
[...]
Post by 王翔
coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock starting...
Boot mode: 15
Couldn't load romstage.
Hmm, this looks like a bug.



Jonathan NeuschÀfer
Jonathan Neuschäfer
2018-12-01 13:29:24 UTC
Permalink
Hi again,
coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock starting...
Boot mode: 15
Couldn't load romstage.
I just tried the same version (coreboot-4.8-2282-gc88828daeb), and it
worked, both with a 1 MiB coreboot image and a 32 MiB coreboot image:

coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock starting...
Boot mode: 15
CBFS: 'Master Header Locator' located CBFS at [20100:2000000)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 2dca


CBMEM:ot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 romstage starting...
IMD: root @ 000000027ffff000 254 entries.
IMD: root @ 000000027fffec00 62 entries.
CBFS: 'Master Header Locator' located CBFS at [20100:2000000)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 2ec0 size 532f


coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 ramstage starting...
BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 1
BS: BS_DEV_INIT_CHIPS times (us): entry 1 run 0 exit 0
Enumerating buses...
CPU_CLUSTER: 0 enabled
scan_bus: scanning of bus Root Device took 2050 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 1 run 9289 exit 1
Allocating resources...
Reading resources...
CPU_CLUSTER: 0 missing read_resources
Done reading resources.
Setting resources...
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 16149 exit 0
Enabling resources...
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 2605 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 1910 usecs
Devices initialized
BS: BS_DEV_INIT times (us): entry 0 run 9464 exit 0
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 3473 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
Writing coreboot table at 0x27ffdc000
0. 0000000080000000-0000000080011fff: RAMSTAGE
1. 0000000080012000-000000008003ffff: RAM
2. 0000000080040000-0000000080044fff: RAMSTAGE
3. 0000000080045000-000000027ffdbfff: RAM
4. 000000027ffdc000-000000027fffffff: CONFIGURATION TABLES

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080000de2
Bad address: 000000027ffdc0f4
Stored ra: 0000000080000d36
Stored sp: 0000000080040ec8
CBFS: 'Master Header Locator' located CBFS at [20100:2000000)

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080000d6a
Bad address: 000000027ffdc10c
Stored ra: 0000000080000d66
Stored sp: 0000000080040ec8

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080000d6e
Bad address: 000000027ffdc114
Stored ra: 0000000080000d66
Stored sp: 0000000080040ec8

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080000d74
Bad address: 000000027ffdc11c
Stored ra: 0000000080000d66
Stored sp: 0000000080040ec8

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080000d7e
Bad address: 000000027ffdc0fc
Stored ra: 0000000080000d66
Stored sp: 0000000080040ec8

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080000d82
Bad address: 000000027ffdc104
Stored ra: 0000000080000d66
Stored sp: 0000000080040ec8
FMAP: Found "FLASH" version 1.1 at 20000.
FMAP: base = 0 size = 2000000 #areas = 4

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080000d8e
Bad address: 000000027ffdc104
Stored ra: 0000000080000d8a
Stored sp: 0000000080040ec8

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080001c68
Bad address: 000000027ffdc124
Stored ra: 0000000080001c66
Stored sp: 0000000080040e58

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080001c72
Bad address: 000000027ffdc12c
Stored ra: 0000000080001c72
Stored sp: 0000000080040e58

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080001c68
Bad address: 000000027ffdc13c
Stored ra: 0000000080001c66
Stored sp: 0000000080040e58

Exception: Store address misaligned
Previous mode: machine
Bad instruction pc: 0000000080001c72
Bad address: 000000027ffdc144
Stored ra: 0000000080001c72
Stored sp: 0000000080040e58
Wrote coreboot table at: 000000027ffdc000, 0x13c bytes, checksum fd30
coreboot table: 340 bytes.
IMD ROOT 0. 000000027ffff000 00001000
IMD SMALL 1. 000000027fffe000 00001000
CONSOLE 2. 000000027ffde000 00020000
COREBOOT 3. 000000027ffdc000 00002000
IMD small region:
IMD ROOT 0. 000000027fffec00 00000400
BS: BS_WRITE_TABLES times (us): entry 0 run 285035 exit 0
CBFS: 'Master Header Locator' located CBFS at [20100:2000000)
CBFS: Locating 'fallback/payload'
CBFS: 'fallback/payload' not found.
Payload not loaded.


One thing I did differently was to program the flash via OpenOCD[1],
rather than from Linux like you did it. Maybe something is broken in
Linux or flashcp?


Jonathan


[1]: https://doc.coreboot.org/mainboard/sifive/hifive-unleashed.html#usb-jtag
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