Discussion:
[AMD family16h] What need to be done in coreboot to support the Virtual Wire mode
(too old to reply)
Zheng Bao
2018-10-22 16:02:37 UTC
Permalink
Hi, all,
I need to support VxWorks in Virtual Wire mode. The code is stable in coreboot.org for a long time which supports
Windows and Linux.
I add code to set the Interrupt Line in PciConfiguration space.
What else needs to be done?

Zheng
Marc Jones
2018-10-22 23:57:31 UTC
Permalink
Does VxWorks use the ACPI tables for IRQ routing? You might need that.

Marc


On Mon, Oct 22, 2018 at 10:03 AM Zheng Bao <***@hotmail.com> wrote:

> Hi, all,
> I need to support VxWorks in Virtual Wire mode. The code is stable in
> coreboot.org for a long time which supports
> Windows and Linux.
> I add code to set the Interrupt Line in PciConfiguration space.
> What else needs to be done?
>
> Zheng
> --
> coreboot mailing list: ***@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot

--
http://marcjonesconsulting.com
Rudolf Marek
2018-10-23 08:36:06 UTC
Permalink
Hi,

Dne 23. 10. 18 v 1:57 Marc Jones napsal(a):
> Does VxWorks use the ACPI tables for IRQ routing? You might need that.

Yes good question. Usually OS uses ACPI, or MPTable or what BIOS provided in
the PCI device itself.

It seems because you are asking for the virtual wire mode IOAPIC is not supported and legacy PIC mode
maybe needed?

Does this OS configure LINT0 for ExtINT on at least one CPU? (this is how virtual wire can be implemented)

Or second way to do that, is to program IO-APIC 0 or 2 depending on chipset to ExtInt. This will cause PIC interrupts
to be delivered to the CPU.

Please note that for PCI devices you also need to program PCI IRQ router and ELCR register if you are going to use the PIC mode,

Thanks
Rudolf


--
coreboot mailing list: ***@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot
Zheng Bao
2018-10-25 07:17:38 UTC
Permalink
I tried AMI and it works.

It seems that VxWorks does not use ACPI.
Mptable and PCI interrupt Line instead.
I copy all the mptable and PCI configuration space from AMI.
Now SATA can work. But PCIe Networks Card can not work.

Any more ideas? Thanks.

Zheng

________________________________
From: coreboot <coreboot-***@coreboot.org> on behalf of Rudolf Marek <***@assembler.cz>
Sent: Tuesday, October 23, 2018 8:36 AM
To: ***@coreboot.org
Subject: Re: [coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

Hi,

Dne 23. 10. 18 v 1:57 Marc Jones napsal(a):
> Does VxWorks use the ACPI tables for IRQ routing? You might need that.

Yes good question. Usually OS uses ACPI, or MPTable or what BIOS provided in
the PCI device itself.

It seems because you are asking for the virtual wire mode IOAPIC is not supported and legacy PIC mode
maybe needed?

Does this OS configure LINT0 for ExtINT on at least one CPU? (this is how virtual wire can be implemented)

Or second way to do that, is to program IO-APIC 0 or 2 depending on chipset to ExtInt. This will cause PIC interrupts
to be delivered to the CPU.

Please note that for PCI devices you also need to program PCI IRQ router and ELCR register if you are going to use the PIC mode,

Thanks
Rudolf


--
coreboot mailing list: ***@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot
Rudolf Marek
2018-10-26 20:06:21 UTC
Permalink
Hi,

Dne 25. 10. 18 v 9:17 Zheng Bao napsal(a):
> Any more ideas? Thanks.

Maybe the bus topology is different in coreboot. It would explain why SATA works, because it is on bus 0.

Thanks,
Rudolf


--
coreboot mailing list: ***@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot
Zheng Bao
2018-10-27 05:18:03 UTC
Permalink
Solved. Not know why.

set IoapicSbFeatureEn=1.

Zheng
________________________________
From: Rudolf Marek <***@assembler.cz>
Sent: Friday, October 26, 2018 8:06 PM
To: Zheng Bao; ***@coreboot.org
Subject: Re: [coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

Hi,

Dne 25. 10. 18 v 9:17 Zheng Bao napsal(a):
> Any more ideas? Thanks.

Maybe the bus topology is different in coreboot. It would explain why SATA works, because it is on bus 0.

Thanks,
Rudolf
Loading...