[coreboot] FSP settings according to decode-dimms

[Zvi Vered]

Hello,

Following is a partial output of decode-dimms:
-------------------------------------------------------------------------
Module Type 72b-SO-UDIMM
....
Maximum module speed 1333 MHz
Size 4096 MB
Banks x Rows x Columns x Bits 8 x 16 x 10 x 64
Ranks 1
SDRAM Device Width 8 bits
Bus Width Extension 8 bits
tCL-tRCD-tRP-tRAS 9-9-9-24
Supported CAS Latencies (tCL) 10T, 9T, 8T, 7T, 6T

---=== Timing Parameters ===---
Minimum Write Recovery time (tWR) 15.000 ns
Minimum Row Active to Row Active Delay (tRRD) 6.000 ns
Minimum Active to Auto-Refresh Delay (tRC) 49.125 ns
Minimum Recovery Delay (tRFC) 260.000 ns
Minimum Write to Read CMD Delay (tWTR) 7.500 ns
Minimum Read to Pre-charge CMD Delay (tRTP) 7.500 ns
Minimum Four Activate Window Delay (tFAW) 30.000 ns

Number of SDRAM DIMMs detected and decoded: 1
---------------------------------------------------------------------------------
Following is a partial output of dmidecode:
---------------------------------------------------------------------------------
Handle 0x0011, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000F
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 2048 MB
Form Factor: DIMM
Set: None
Locator: A1_DIMM0
Bank Locator: A1_BANK0
Type: DDR3
Type Detail: Unknown
Speed: 1333 MHz
Manufacturer: A1_Manufacturer0
Serial Number: A1_SerNum0
Asset Tag: A1_AssetTagNum0
Part Number: Array1_PartNumber0
Rank: Unknown
Configured Clock Speed: 1066 MHz
Minimum Voltage: 1.35 V
Maximum Voltage: 1.5 V
Configured Voltage: 1.35 V
-----------------------------------------------------------------------------------------
According to the above output I set the following in BCT:

Enable Memory Down: Disabled
DRAM Speed: 1333
DRAM Type: DDR3
DIMM 0 Enable: Enabled
DIMM 1 Enabled: Disabled
DIMM_DWidth: x8
DIMM Density: 4 Gbit
DIMM_BusWidth: 8 bits
DIMM_Sides: 1 Ranks
tCL: 9
tRP_tRCD: 9
tWR: 15
tWTR: 7
tRRD: 6
tRTP: 7
tFAW: 30

I set DIMM_Density according to DDR's datasheet (MEM4G08D3E/FABG)

Can you please tell if my settings are correct ?
tWTR = 7.5nsec. but BCT gets only integer value.
tRTP = 7.5nsec but BCT gets only integer value.
Configured Clock Speed: 1066 MHz. Is this the speed I should set ?

Thank you,
Zvika

[Nico Huber]

Hi Zvi,

I assume you still ask for the BayTrail FSP, correct? You didn't
mention it in your last mails.

Post by Zvi Vered
Module Type 72b-SO-UDIMM

This suggests that you have a DIMM? i.e. a module, not soldered down
DRAM, is that correct?

Post by Zvi Vered
Enable Memory Down: Disabled
DRAM Speed: 1333
...

These settings all live in a struct called MEMORY_DOWN_DATA. I don't
know for sure, but I assume with "EnableMemoryDown Disabled" you disable
the whole struct. I can also not find a single board in coreboot that
sets `EnableMemoryDown` explicitly to 0.

Maybe one of the FSP BayTrail maintainers can clarify? or even provide
some documentation?

Also, please use coreboot's infrastructure to set these things from your
mainboard's `romstage.c` or `devicetree.cb`. If you want help with BCT,
better ask Intel.

If you have a real DIMM module with an SPD that can be read from SMBus,
I would try setting `PcdMrcInitSPDAddr1`. Be aware that it expects the
SMBus address shifted left by 1 (e.g. the 7-bit address 0x50 would be
0xa0 for FSP). You can set it from the devicetree, for examples check
the source, e.g.:
git grep '"PcdMrcInitSPDAddr1"'

If you don't have a module but soldered down memory, here's an example
how to map the values from your SPD to FSP: `mainboard/siemens/mc_tcu3/
romstage.c`.

I'm not sure if this works though, as this board also sets
`PcdMrcInitSPDAddr*` in the devicetree, which confuses me (same for
intel/minnowmax, Intel maintainers?).

Hope that helps,
Nico

[Zvi Vered]

Hi Nico, All,

The DRAM is soldered. There is no DIMM module.
After changing to "Enable Memory Down = Enabled" I got post code 0x92 just
before calling to:
FspInitApi(&FspInitParams) in src/drivers/intel/fsp1_0

From there, romstage_main_continue in soc/intel/fsp_baytrail/romstage
should be called but it does not happen.
Any ideas why ?

Thank you,
Zvika

Post by Nico Huber
Hi Zvi,
I assume you still ask for the BayTrail FSP, correct? You didn't
mention it in your last mails.

Post by Zvi Vered
Module Type 72b-SO-UDIMM

This suggests that you have a DIMM? i.e. a module, not soldered down
DRAM, is that correct?

Post by Zvi Vered
Enable Memory Down: Disabled
DRAM Speed: 1333
...

These settings all live in a struct called MEMORY_DOWN_DATA. I don't
know for sure, but I assume with "EnableMemoryDown Disabled" you disable
the whole struct. I can also not find a single board in coreboot that
sets `EnableMemoryDown` explicitly to 0.
Maybe one of the FSP BayTrail maintainers can clarify? or even provide
some documentation?
Also, please use coreboot's infrastructure to set these things from your
mainboard's `romstage.c` or `devicetree.cb`. If you want help with BCT,
better ask Intel.
If you have a real DIMM module with an SPD that can be read from SMBus,
I would try setting `PcdMrcInitSPDAddr1`. Be aware that it expects the
SMBus address shifted left by 1 (e.g. the 7-bit address 0x50 would be
0xa0 for FSP). You can set it from the devicetree, for examples check
git grep '"PcdMrcInitSPDAddr1"'
If you don't have a module but soldered down memory, here's an example
how to map the values from your SPD to FSP: `mainboard/siemens/mc_tcu3/
romstage.c`.
I'm not sure if this works though, as this board also sets
`PcdMrcInitSPDAddr*` in the devicetree, which confuses me (same for
intel/minnowmax, Intel maintainers?).
Hope that helps,
Nico