[coreboot] GSOC submission

[Arthur Heymans]

Hi

It has been a few years since coreboot (or flashrom) applied for Google
Summer Of Code. In 2019 the applications for organizations open on
january 2019 and student applications on March 25.

I think it would be great if the coreboot project could apply in 2019,
as doing so has been very valuable for the project in the past.

I don't really know the full set of requirements and procedures, but I
think it could be worthwhile to start thinking about project ideas.

A few ideas were already suggested on IRC on freenode #coreboot:
- 64bit x86 ramstage (hard)
- documented microcode update methods and write a tool that generates a
webpage which microcodes are included in coreboot (easy)
- nvidea optimus support (medium)
- QEMU power9 support / initial openpower support (hard I guess?)
- Rework device resource allocation to support 64bit BAR (relatively
hard)

Any ideas or suggestions?

Kind regards

Arthur Heymans

[T***@gmx.com]

Post by Arthur Heymans
Hi
It has been a few years since coreboot (or flashrom) applied for Google
Summer Of Code. In 2019 the applications for organizations open on
january 2019 and student applications on March 25.
I think it would be great if the coreboot project could apply in 2019,
as doing so has been very valuable for the project in the past.
I don't really know the full set of requirements and procedures, but I
think it could be worthwhile to start thinking about project ideas.
- 64bit x86 ramstage (hard)
- documented microcode update methods and write a tool that generates a
webpage which microcodes are included in coreboot (easy)
- nvidea optimus support (medium)
- QEMU power9 support / initial openpower support (hard I guess?)

IMO not worth it since TALOS 2/Blackbird already have owner controlled
open source firmware directly from the factory so do various other
OpenPOWER machines.

Post by Arthur Heymans
- Rework device resource allocation to support 64bit BAR (relatively
hard)

Agreed this would be super great. I get plenty of failed to assign BAR
errors on my coreboot machines and my system doesn't work properly due
to not enough BAR space unless the PCI-e cards are inserted in a
specific order.

Post by Arthur Heymans
Any ideas or suggestions?

* SR-IOV/ARI support on the SR56xx AMD chipset code fam15h native init
coreboot so boards KGPE-D16/KCMA-D8.

According to the chipset documentation the chipsets support it and
various other advanced PCI-e features that aren't activated so it should
be easy but I can't figure out how to do it.

* Activating the IOMMU in coreboot on boards that support it.

[Angel Pons]

Hello,

Post by T***@gmx.com

Post by Arthur Heymans
Hi
It has been a few years since coreboot (or flashrom) applied for Google
Summer Of Code. In 2019 the applications for organizations open on
january 2019 and student applications on March 25.
I think it would be great if the coreboot project could apply in 2019,
as doing so has been very valuable for the project in the past.
I don't really know the full set of requirements and procedures, but I
think it could be worthwhile to start thinking about project ideas.
- 64bit x86 ramstage (hard)
- documented microcode update methods and write a tool that generates a
webpage which microcodes are included in coreboot (easy)
- nvidea optimus support (medium)
- QEMU power9 support / initial openpower support (hard I guess?)

IMO not worth it since TALOS 2/Blackbird already have owner controlled
open source firmware directly from the factory so do various other
OpenPOWER machines.

Do you refer to only the last point (qemu POWER9) or the whole quoted text?
Timothy Pearson expressed interest in getting coreboot on POWER9, and gave
a few reasons:
- Speed: coreboot will be faster
- DDR4: coreboot devs can see how DDR4 bringup is done
- coreboot can be in some other device than just old stuff / chromedevices.

Best regards,

Angel Pons

[Timothy Pearson]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

On the POWER9 topic, it might even be possible to skip QEMU and go
straight to hardware. My current understanding is that the FSI drivers
in OpenBMC allow single stepping of the CPU and dumping of registers,
without any other hardware being required to access those features.
There's also a built-in firmware-from-RAM loader on the BMC side, so
iterating changes should be fairly easy.

Raptor would be also willing to donate a number of POWER9 development
kits in support of a coreboot port, if there's interest.

I was planning to apply this year, let's see what comes of it.
Thank you for the list of project ideas, very valuable!
Patrick
Am Do., 29. Nov. 2018 um 15:04 Uhr schrieb Arthur Heymans
Hi
It has been a few years since coreboot (or flashrom) applied for Google
Summer Of Code. In 2019 the applications for organizations open on
january 2019 and student applications on March 25.
I think it would be great if the coreboot project could apply in 2019,
as doing so has been very valuable for the project in the past.
I don't really know the full set of requirements and procedures, but I
think it could be worthwhile to start thinking about project ideas.
- 64bit x86 ramstage (hard)
- documented microcode update methods and write a tool that generates a
webpage which microcodes are included in coreboot (easy)
- nvidea optimus support (medium)
- QEMU power9 support / initial openpower support (hard I guess?)
- Rework device resource allocation to support 64bit BAR (relatively
hard)
Any ideas or suggestions?
Kind regards
Arthur Heymans
--
https://mail.coreboot.org/mailman/listinfo/coreboot
--
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Hamburg
Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

- --
Timothy Pearson
Raptor Engineering
[phone] (direct line)
[phone] (switchboard)
https://www.raptorengineering.com
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQEcBAEBCAAGBQJcAGM2AAoJEK+E3vEXDOFbnHsIALfp6X1pdLwDNOoUXyIfWN0j
icD+AvFJjZ0mrUwwGDyuo0e8uxYCdzDHsrLS0TMNDIhYEKJ6vkvwD1hl1DnV5VTZ
Kmxpx7MUFmyGCYu5aGT66GqJraYM5o4qchc07D4tNZ+ZBLsk6CsGu4zUjPkGsv+x
0jCLkOrBzkx01ydPY3FYSUGs9bo+1G6CZ6sphBwotFkBury9y/lqr3GNcqGll/uK
Lmdv2oZ36q5BmzRUvRWJLpw5VjNhsNnsMlRsbzbC6m7FF9Roh1pgAe/A0XlX4tNp
flrJ1OdCWs/Mb7OI8DkEYzL+rILhlZDdg7RyWdYh8hkwOrGxGjMcwI9Oqs/+xZg=
=bW2N
-----END PGP SIGNATURE-----

[Julius Werner]

Post by Arthur Heymans
- QEMU power9 support / initial openpower support (hard I guess?)

How about QEMU MIPS support? We have all the MIPS architecture code in
coreboot, but it's falling into complete disrepair because the only
supported board is some old aborted Google project that nobody has
hardware for anymore. It would be a shame if we eventually just have
to throw the whole architecture port away because we have no way to
test it anymore. Getting a working emulation board up for it would
mean that we can keep it alive and healthy until the next time we add
an actual MIPS board.