[coreboot] Using LPC bus serial interrupts

[yanvasilij yan]

Hello!


I am trying to use LPC wire on my Intel Atom E3800 based board for
communication with my custom FPGA device. There is sja1000 CAN transivere
realized on this device. So I can work with this device by polling with no
problem. But for some strange reason, I don’t get interrupts from this
device. I see by oscilloscope serial irq requests from CPU and the device
is response, but my OS (Linux) does not get this interrupts. Here my board
directory https://github.com/yanvasilij/nefteavtomatika.

I think I have a similar problem like this
https://mail.coreboot.org/pipermail/coreboot/2016-January/080839.html. But
my device use IRQ7, not IRQ4.

So I made like described here
https://mail.coreboot.org/pipermail/coreboot/2016-January/080848.html.

There are adviced to me to describe my LPC device in devicetree. But should
I realy to do it, if I working with LPC bus directly from Linux?

What am I doing wrong?

What am I doing wrong? May be I have a problem with IRQ route?

Linux dmesg output and .config are in attachments.

Regards
Vasily
ПреЎварОтельМый прПсЌПтр файла dmesg.txt
dmesg.txt
36 KB
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ПреЎварОтельМый прПсЌПтр файла .config
.config
20 KB
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[Tony Marchini]

Assuming you are generating the serial IRQ stream to the CPU correctly, if you are using IRQ7 , then you need to make sure the IRQ 7 isn't being assigned to any PCI devices. You need to eliminate and IRQs you want from the LPC from the PIRQ table.

There are also some configuration of the 8259 for level vs edge triggering.

Also, it is handy for the SERIRQ to be in continuous mode.

Sincerely,
Anthony A. Marchini
Software Engineer

[yanvasilij yan]

Hello, Tony Marchini! Thank you for response!

To configure LPC I made:

1) Added line to devicetree:
...
device pci 1f.0 on end # 8086 0F1C - LPC bridge
...

2) Enabled alternative function for gpio pins:

GPIO_FUNC1, // GPIO_S0_SC[042] - ILB_LPC_AD[0]
GPIO_FUNC1, // GPIO_S0_SC[043] - ILB_LPC_AD[1]
GPIO_FUNC1, // GPIO_S0_SC[044] - ILB_LPC_AD[2]
GPIO_FUNC1, // GPIO_S0_SC[045] - ILB_LPC_AD[3]
GPIO_FUNC1, // GPIO_S0_SC[046] - ILB_LPC_FRAME
GPIO_FUNC1, // GPIO_S0_SC[047] - ILB_LPC_CLK[0]
GPIO_NC, // GPIO_S0_SC[048] - No Connect
GPIO_FUNC1, // GPIO_S0_SC[049] - ILB_LPC_CLKRUN
GPIO_FUNC1, // GPIO_S0_SC[050] - ILB_LPC_SERIRQ

3) irqrout.h (was taken from MinnowMax):

#define BRIDGE1_DEV PCIE_DEV
#define PCIE_BRIDGE_IRQ_ROUTES \
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)

#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)

#define PIRQ_PIC_ROUTES \
PIRQ_PIC(A, 3), \
PIRQ_PIC(B, 5), \
PIRQ_PIC(C, 7), \
PIRQ_PIC(D, 10), \
PIRQ_PIC(E, 11), \
PIRQ_PIC(F, 12), \
PIRQ_PIC(G, 14), \
PIRQ_PIC(H, 15)

4) In /coreboot/src/soc/intel/fsp_baytrail/southcluster.c
enabled SETUPSERIQ and CONFIG_SERIRQ_CONTINUOUS_MODE to 1.

Does it enought?

Regrads,
Vasily

[Nico Huber]

Hi Vasily,

Post by yanvasilij yan
PIRQ_PIC(C, 7), \

this is likely the culprit. Tony mentioned you must make sure that
IRQ7 isn't used by PCI devices. Which was also my original suspicion,
but the datasheet doesn't mention that :-/

Nico