Discussion:
Configuration for Apollo Lake FSP (Github/MR5)
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Nico Huber
2018-11-19 09:37:15 UTC
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Hi,

has anyone made good or bad experience with the Apollo Lake FSP
currently on Github (it's the MR5, afaict)? FSP-M never returns
for me and I have no post-code display :-/

I tried both XIP and loading into CAR, same result. Maybe it's
still something wrong with my configuration. If anybody had suc-
cess with this binary, please share your `.config`.

My FSP-M UPDs could be wrong as well. But can that result in a
hanging FSP? Do we have to expect undefined behaviour because
of bad memory parameters?

Nico
Nico Huber
2018-11-19 12:42:19 UTC
Permalink
Post by Nico Huber
My FSP-M UPDs could be wrong as well. But can that result in a
hanging FSP? Do we have to expect undefined behaviour because
of bad memory parameters?
Solved it. My board has an SPD and I was missing the pad configuration
for SMBus. Though, I wouldn't think that FSP should hang there...

Thanks anyway :)
Nico
Alexey Borovikov
2018-11-20 18:13:38 UTC
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Hi, Nico!
Is there an external superio on your board?
At the moment I am trying to solve the problem of initializing the external superio chip for the SOC Baytrail processor, but so far without success.
Nico Huber
2018-11-20 21:38:40 UTC
Permalink
Hi Alexey,
Post by Alexey Borovikov
Is there an external superio on your board?
yes, kind of. There's an FPGA attached to the LPC bus that exposes UARTs
among some other interfaces.
Post by Alexey Borovikov
At the moment I am trying to solve the problem of initializing the
external superio chip for the SOC Baytrail processor, but so far without
success.
I don't know the Bay Trail SoC. But my most common advice might help
here: Do all pin/pad configuration (e.g. GPIOs) first. This seems to
affect even very common connections on Intel's Atom SoCs. What I just
learned during the past few days: LPC isn't the default configuration
on Apollo Lake, and the same seems to be true for Bay Trail.

Nico
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Alexey Borovikov
2018-12-04 19:23:10 UTC
Permalink
Maybe the problem is that SERIRQ are disabled? Why is it necessary to use
SERIRQ for BayTrail when connecting superio to lpc bus?

-----Исходное сообщение-----
From: Nico Huber
Sent: Wednesday, November 21, 2018 12:38 AM
To: Alexey Borovikov
Cc: ***@coreboot.org
Subject: BayTrail LPC configuration (was: Re: Configuration for Apollo Lake
FSP (Github/MR5))

Hi Alexey,
Post by Alexey Borovikov
Is there an external superio on your board?
yes, kind of. There's an FPGA attached to the LPC bus that exposes UARTs
among some other interfaces.
Post by Alexey Borovikov
At the moment I am trying to solve the problem of initializing the
external superio chip for the SOC Baytrail processor, but so far without
success.
I don't know the Bay Trail SoC. But my most common advice might help
here: Do all pin/pad configuration (e.g. GPIOs) first. This seems to
affect even very common connections on Intel's Atom SoCs. What I just
learned during the past few days: LPC isn't the default configuration
on Apollo Lake, and the same seems to be true for Bay Trail.

Nico
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coreboot mailing list: ***@coreboot.org
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