[coreboot] [SMSC SCH3114] Super I/O issues

[Konstantin Novikov]

Hello!

I'm working on BayTrail SoC with Super I/O (SMSC SCH 3114). Now Super I/O
is my big headache. Is anybody knows, why a PS/2 keyboard doesn't works
when 'PS/2 keyboard initialized' printed in debug console?
I'm really sure that I'm found it on PCI bus (values from Super I/O
registers' are correct). I see some allocated resources for it in debug
console log. But I can't use COM ports and PS/2 devices.
I'm really unsure, that I'm configured a device tree well. My main
missunderstanding: where can I find IRQs for LDNs? Didn't found this
information in a Super I/O's datasheet. Is it "any free" value for IRQ? Or
I must search information about it in BayTrail datasheet?

Thank you all (log attached).

Novikov Konstantin.

[Alexander Couzens]

Hi Konstantin,

the IRQ are usually freely configurable via the LDN.
Using the lower bits of 0x70h is quite common to select the IRQ.

The SuperIO is connected via LPC, which supports all legacy IRQs by
Serial-IRQ.
Further, depending on the Chipset, it must allow to receive the IRQs
over the SerIRQ line of the LPC.

Best Regards,
lynxis

[Konstantin Novikov]

So, we're now very close to the end. Our COM and PS/2 works in SeaBIOS, but
doesn't works in OS Linux.
Thanks Alexander for his help, It was really all about SerIRQ.

Repeating: we have SoC Intel Baytrail with Atom E3845 CPU and Super I/O
SMSC 3114. And our problem was in broken PS/2 and COM-ports.

COM-port:
At first of all, we're commented out this line in soc/romstage/romstage.c:
byt_config_com1_and_enable(); - from main(...) function.

And our COM1 sent for pretty small piece of coreboot log for us. But after
few lines he died somewhere in FSP.
We're thought, FSP made byt_config_com1_and_enable's analogue and
initialized Legacy UART again. So, were wrote little function:

void byt_config_com1_and_disable(void)
{
uint32_t reg;

reg = pci_read_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT);
reg &= 0xFFFFFFF0;
reg |= 0x02; // Set uncorrect addresses for COMA and COMB
pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
}

And now we're see full coreboot log (+SeaBIOS log too).

What's about PS/2? We're found sc_enable_serial_irqs function in
soc/intel/fsp_baytrail/southcluster.c with comments about suspicious
interrupts by PS/2. It's body was empty because of define.
So, we're defined that (#define SETUPSERIQ) and added this option in our
KConfig (select CONFIG_SERIRQ_CONTINUOUS_MODE). After all, PS/2 keyboard is
works in SeaBIOS.

But know we're confused by OS Linux (latest Lubuntu). COM and PS/2 doesn't
works, we're see "PS/2 controller not found" in dmesg.
Why It's works in SeaBIOS and isn''t works in OS? Is it because of
uncorrect IRQs or we need correct our asl code?

Thank you all for your help and attention, Coreboot society!

Post by Alexander Couzens
Hi Konstantin,
the IRQ are usually freely configurable via the LDN.
Using the lower bits of 0x70h is quite common to select the IRQ.
The SuperIO is connected via LPC, which supports all legacy IRQs by
Serial-IRQ.
Further, depending on the Chipset, it must allow to receive the IRQs
over the SerIRQ line of the LPC.
Best Regards,
lynxis
--
Alexander Couzens
mobile: [phone]
gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604

[Alexander Couzens]

Hi Kkonstantin,

just by any chance, do you tried to use baytrail and _not_ fsp_baytrail?

best,
lynxis

[Alexey Borovikov]

In the repository Coreboot, I could not find a motherboard with a SOC Baytrail or analogue with external superio. Can someone tell me, what motherboard with SOC processor I can take as example of work LPC with superio chip?