coreboot@coreboot.org

1

reply

CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:

started 2018-10-31 06:08:51 UTC

2018-10-31 11:13:42 UTC

Lance Zhao

2

replies

Reducing FSP performance time

started 2018-10-29 20:22:03 UTC

2018-10-30 15:29:07 UTC

Nico Huber

0

replies

Revisiting an old project from the FreeBIOS days

started 2018-10-29 05:36:19 UTC

2018-10-29 05:36:19 UTC

Gregg Levine

5

replies

[AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

started 2018-10-22 21:02:37 UTC

2018-10-27 10:18:03 UTC

Zheng Bao

0

replies

New Defects reported by Coverity Scan for coreboot

started 2018-10-27 09:40:23 UTC

2018-10-27 09:40:23 UTC

s***@coverity.com

2

replies

Basic bios info

started 2018-10-24 15:07:10 UTC

2018-10-25 06:07:06 UTC

m***@tutanota.com

0

replies

cbfstool issue

started 2018-10-24 20:28:39 UTC

2018-10-24 20:28:39 UTC

Wim Vervoorn

1

reply

Contribution to coreboot board status

started 2018-10-23 13:16:57 UTC

2018-10-24 13:31:55 UTC

Sven Dreyer

7

replies

T520 vs. T530

started 2018-10-23 12:02:54 UTC

2018-10-24 03:14:35 UTC

Nico Huber

0

replies

F2A85M board

started 2018-10-21 14:44:52 UTC

2018-10-21 14:44:52 UTC

kinky_nekoboi

0

replies

New Defects reported by Coverity Scan for coreboot

started 2018-10-19 19:31:57 UTC

2018-10-19 19:31:57 UTC

s***@coverity.com

0

replies

FSP integration

started 2018-10-19 08:12:23 UTC

2018-10-19 08:12:23 UTC

Zvi Vered

3

replies

Modifying FSP in Binary Configuration Tool (BCT)

started 2018-10-12 21:29:07 UTC

2018-10-18 02:31:47 UTC

Zvi Vered

43

replies

SPI controller and Lock bits

started 2018-09-26 04:30:54 UTC

2018-10-18 02:07:19 UTC

Youness Alaoui

11

replies

Wired problems with Intel skylake based board

started 2018-09-24 16:04:50 UTC

2018-10-16 21:18:16 UTC

Nico Huber

4

replies

MRC in coreboot

started 2018-09-05 18:00:48 UTC

2018-10-16 14:24:47 UTC

Peter Stuge

1

reply

Watchdog timer (WDT) support on Kabylake w/FSP2.0

started 2018-10-10 22:36:29 UTC

2018-10-16 02:25:38 UTC

Solanki, Naresh

0

replies

What determines PCI-e capabilities per chipset in coreboot? (ie: pcie register space)

started 2018-10-16 02:25:31 UTC

2018-10-16 02:25:31 UTC

T***@gmx.com

22

replies

Source code for "Intel Firmware"

started 2018-10-06 09:50:18 UTC

2018-10-14 21:55:21 UTC

Nico Huber

2

replies

New Defects reported by Coverity Scan for coreboot

started 2018-10-05 19:25:54 UTC

2018-10-12 19:28:38 UTC

s***@coverity.com

1

reply

intel/i82801dx SMM memory size?

started 2018-10-03 08:59:08 UTC

2018-10-11 16:06:09 UTC

Kyösti Mälkki

0

replies

Post code 0xCE: coreboot.rom with fsp

started 2018-10-11 01:38:41 UTC

2018-10-11 01:38:41 UTC

Zvi Vered

0

replies

post code 0xb0 after coreboot.rom BIOs burn

started 2018-10-10 01:59:39 UTC

2018-10-10 01:59:39 UTC

Zvi Vered

1

reply

Change superio in "Bayley Bay FSP-based CRB"

started 2018-10-08 02:02:14 UTC

2018-10-09 02:47:47 UTC

Zvi Vered

4

replies

Lenovo G505S - spkmodem console sound, is correct? Please listen and tell

started 2018-09-27 03:22:49 UTC

2018-10-08 19:53:22 UTC

Denis 'GNUtoo' Carikli

4

replies

USB 2.0 EHCI debug dongle doesn't print logs (at Lenovo G505S)

started 2018-09-29 02:50:18 UTC

2018-10-08 19:37:17 UTC

Denis 'GNUtoo' Carikli

2

replies

Bootblock CMOS default and the checksum algo

started 2018-10-07 07:27:11 UTC

2018-10-07 21:58:28 UTC

William McCall

1

reply

lower memory performance with coreboot on KGPE-D16

started 2018-10-04 13:23:24 UTC

2018-10-07 12:12:29 UTC

Iru Cai

1

reply

current state of board/f2a85m

started 2018-10-06 17:23:34 UTC

2018-10-07 00:27:59 UTC

David Hendricks

11

replies

Burn 2MB coreboot.rom on 8MB flash chip

started 2018-09-25 00:18:59 UTC

2018-10-06 15:15:58 UTC

Nico Huber