Mailing List:
coreboot@coreboot.org
Add newDisplay options
1
reply
CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:
started 2018-10-31 01:08:51 UTC
2018-10-31 06:13:42 UTC
Lance Zhao
2
replies
Reducing FSP performance time
started 2018-10-29 15:22:03 UTC
2018-10-30 10:29:07 UTC
Nico Huber
0
replies
Revisiting an old project from the FreeBIOS days
started 2018-10-29 00:36:19 UTC
2018-10-29 00:36:19 UTC
Gregg Levine
5
replies
[AMD family16h] What need to be done in coreboot to support the Virtual Wire mode
started 2018-10-22 16:02:37 UTC
2018-10-27 05:18:03 UTC
Zheng Bao
0
replies
New Defects reported by Coverity Scan for coreboot
started 2018-10-27 04:40:23 UTC
2018-10-27 04:40:23 UTC
s***@coverity.com
2
replies
Basic bios info
started 2018-10-24 10:07:10 UTC
2018-10-25 01:07:06 UTC
m***@tutanota.com
0
replies
cbfstool issue
started 2018-10-24 15:28:39 UTC
2018-10-24 15:28:39 UTC
Wim Vervoorn
1
reply
Contribution to coreboot board status
started 2018-10-23 08:16:57 UTC
2018-10-24 08:31:55 UTC
Sven Dreyer
7
replies
T520 vs. T530
started 2018-10-23 07:02:54 UTC
2018-10-23 22:14:35 UTC
Nico Huber
0
replies
F2A85M board
started 2018-10-21 09:44:52 UTC
2018-10-21 09:44:52 UTC
kinky_nekoboi
0
replies
New Defects reported by Coverity Scan for coreboot
started 2018-10-19 14:31:57 UTC
2018-10-19 14:31:57 UTC
s***@coverity.com
0
replies
FSP integration
started 2018-10-19 03:12:23 UTC
2018-10-19 03:12:23 UTC
Zvi Vered
3
replies
Modifying FSP in Binary Configuration Tool (BCT)
started 2018-10-12 16:29:07 UTC
2018-10-17 21:31:47 UTC
Zvi Vered
43
replies
SPI controller and Lock bits
started 2018-09-25 23:30:54 UTC
2018-10-17 21:07:19 UTC
Youness Alaoui
11
replies
Wired problems with Intel skylake based board
started 2018-09-24 11:04:50 UTC
2018-10-16 16:18:16 UTC
Nico Huber
4
replies
MRC in coreboot
started 2018-09-05 13:00:48 UTC
2018-10-16 09:24:47 UTC
Peter Stuge
1
reply
Watchdog timer (WDT) support on Kabylake w/FSP2.0
started 2018-10-10 17:36:29 UTC
2018-10-15 21:25:38 UTC
Solanki, Naresh
0
replies
What determines PCI-e capabilities per chipset in coreboot? (ie: pcie register space)
started 2018-10-15 21:25:31 UTC
2018-10-15 21:25:31 UTC
T***@gmx.com
22
replies
Source code for "Intel Firmware"
started 2018-10-06 04:50:18 UTC
2018-10-14 16:55:21 UTC
Nico Huber
2
replies
New Defects reported by Coverity Scan for coreboot
started 2018-10-05 14:25:54 UTC
2018-10-12 14:28:38 UTC
s***@coverity.com
1
reply
intel/i82801dx SMM memory size?
started 2018-10-03 03:59:08 UTC
2018-10-11 11:06:09 UTC
Kyösti Mälkki
0
replies
Post code 0xCE: coreboot.rom with fsp
started 2018-10-10 20:38:41 UTC
2018-10-10 20:38:41 UTC
Zvi Vered
0
replies
post code 0xb0 after coreboot.rom BIOs burn
started 2018-10-09 20:59:39 UTC
2018-10-09 20:59:39 UTC
Zvi Vered
1
reply
Change superio in "Bayley Bay FSP-based CRB"
started 2018-10-07 21:02:14 UTC
2018-10-08 21:47:47 UTC
Zvi Vered
4
replies
Lenovo G505S - spkmodem console sound, is correct? Please listen and tell
started 2018-09-26 22:22:49 UTC
2018-10-08 14:53:22 UTC
Denis 'GNUtoo' Carikli
4
replies
USB 2.0 EHCI debug dongle doesn't print logs (at Lenovo G505S)
started 2018-09-28 21:50:18 UTC
2018-10-08 14:37:17 UTC
Denis 'GNUtoo' Carikli
2
replies
Bootblock CMOS default and the checksum algo
started 2018-10-07 02:27:11 UTC
2018-10-07 16:58:28 UTC
William McCall
1
reply
lower memory performance with coreboot on KGPE-D16
started 2018-10-04 08:23:24 UTC
2018-10-07 07:12:29 UTC
Iru Cai
1
reply
current state of board/f2a85m
started 2018-10-06 12:23:34 UTC
2018-10-06 19:27:59 UTC
David Hendricks
11
replies
Burn 2MB coreboot.rom on 8MB flash chip
started 2018-09-24 19:18:59 UTC
2018-10-06 10:15:58 UTC
Nico Huber
Click to Load More...
Loading...